Applying Asynchronous Techniques to a Viterbi Decoder Design

INTRODUCTION Viterbi decoders are used for decoding convolutional forward error correction codes [ 13 in a large proportion of digital transmission systems including mobile phones and digital television. For portable applications, the battery size and lifetime is of commercial importance as is the size of the electronics. Therefore, a low power, area efficient implementation is of commercial interest as a means of both lowering costs and extending the battery operating time. PREST and Powerpack have been collaborative projects, funded by the EU and EPSRC respectively, which have resulted in different Universities designing low power alternatives to an industry standard Viterbi Decoder [2]. The techniques involved for reducing power from current levels range from circuits and timing strategies to architectures and algorithms.